Priyanka Palaka* and G. Sankara rao
In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chips total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called Stacked LCNMOS for designing CMOS gates.
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