PRINT (ISSN) 2319-1783
ONLINE (ISSN) 2320-1126
ONLINE (ISSN) 2320-1126
A.V.S Naidu* and B. Vijayabhaskar
Abstract:
Barrel shifters are often utilized by embedded digital signal processors and general purpose processors to manipulate data. Barrel shifters are widely used where more than one bit shift operation is required in arithmetic and logical operations. The design of barrel shifter is a most challenging task towards its speed, area and power consumption. Here we are going to implement an 8-bit barrel shifter in the form of two approaches and we are going to analyze the circuits in terms of speed area and power consumption. Here the circuits are implemented and analyzed by using the most popular semi-custom design tool VHDL and will be synthesized by using SPARTAN-3 FPGA.
https://doi.org/10.62226/ijarst20130383
PAGES : 127-129 | 47 VIEWS | 78 DOWNLOADS
A.V.S Naidu* and B. Vijayabhaskar | Implementation of Area Efficient Barrel Shifter | DOI : https://doi.org/10.62226/ijarst20130383
| Journal Frequency: | ISSN 2320-1126, Monthly | |
| Paper Submission: | Throughout the month | |
| Acceptance Notification: | Within 6 days | |
| Subject Areas: | Engineering, Science & Technology | |
| Publishing Model: | Open Access | |
| Publication Fee: | USD 60 USD 50 | |
| Publication Impact Factor: | 6.76 | |
| Certificate Delivery: | Digital |
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