Volume 3, Issue 4

Design of 2-Dimensional Multiplier Using Area efficient and Power Optimization Technique

Author

Kesanakurthi Rajasekhar* and J. Kiran Chandrasekhar

Abstract

Based on the simplification of the addition operations in a low-power bypassing-based multiplier, a low-cost low-power bypassing-based multiplier is proposed. Row-bypassing multiplier, column-bypassing multiplier, 2-Dimensional bypassing multiplier and braun multipliers are implemented in CMOS and GDI technique. By optimizing the transistor size in each stage the power and area are minimized. The results of post-layout simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power. The experimental results show that our proposed low-cost low power multiplier saves hardware cost and reduces the power dissipation.

DOI

https://doi.org/10.62226/ijarst20140444

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