Volume 4, Issue 2

Design of an efficient and faster SDRAM Controller.


P. Sridevi* and B. Venu Gopal


In this paper Double data rate synchronous dynamic (DDR SDRAM)
accessing of memory and controller are designed in such a way that it
supports double data transfer rate. To guarantee that the system works as
intended, the memory controller is configured such that all the real-time
requirements of all sharing applications are satisfied. A fully functional
DDRSDRAM controller is designed to perform Read and Write operations
on both rising and falling edge (DDR) of clock from the memory by using
data path module with double data transfer throughput and bandwidth of the
memory. The implementation uses direct clocking for data capture. To
improve the access speed controller will generate the control signals at high
speed and memory also supposes to access the data very easily. The memory
has been designed to access the data by using the CAS and RAS signals in an
easy way and controller also has been implemented with double data rate.
For a single row different column data can be read at a time so the
improvement of 28.57% in the performance of memory accessing.



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P. Sridevi* and B. Venu Gopal | Design of an efficient and faster SDRAM Controller. | DOI : https://doi.org/10.62226/ijarst20150207

Journal Frequency: ISSN 2320-1126, Monthly
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Acceptance Notification: Within 6 days
Subject Areas: Engineering, Science & Technology
Publishing Model: Open Access
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