Volume 4, Issue 6

Design of a faster 8T SRAM memory cell

Author

S.K.V.Prasad* and Rambabu

Abstract

This paper discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic operations, SNM concept, and write margin of an SRAM are described theoretically as well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. With the write assisted circuit, the implemented memory array successfully performs a write operation, the condition in which the same operation would fail without the write assisted circuit. During the simulation, this write assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAM’s bit- lines. The cost overhead includes chip area, power consumption and chip area.

DOI

https://doi.org/10.62226/ijarst20150651

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